1. Field of the Invention
The present invention relates to semiconductor simulation required in designing and development of semiconductor devices including Large Scale Integrations (LSIs). The present invention relates more specifically to a method and an apparatus for carrying out process simulation to obtain the geometry of semiconductor devices as well as the distribution profiles of impurities and defects in those devices. And the present invention also relates to a method and an apparatus for obtaining device simulation to obtain the electrical characteristics etc. of semiconductor devices based on the output of such process simulation apparatus. Moreover, the present invention relates to a computer memory medium which stores programs for use in such simulation. The present invention relates more specifically to a technology which, in such process simulation and device simulation, easily specifies processes to be optimized, thereby obtaining the optimal conditions for such semiconductor devices.
2. Description of the Related Art
In the design and development of semiconductor devices, conventionally, to decide fabrication processes to realize such semiconductor devices as to meet desired electrical characteristics, a process simulator (process simulation apparatus) and a device simulator (device simulation apparatus) have been employed. The process simulator simulates the process of fabricating those semiconductor devices in order to obtain the geometry of hose devices and the distribution profile of impurities in hose devices. The device simulator simulates the electrical characteristics of those devices.
Actually, first, an appropriate structure of a semiconductor device is roughly selected and designed against prescribed characteristics specifications. Then, process simulation is carried out to realize thus outlined device structure. This process simulation employs a process simulator in such a way that the simulator receives as an input the materials and their fabrication procedure as well as its respective processes conditions, to work out the resultant structure of the semiconductor device. Next, device simulation is carried out by a device simulator employing the obtained structure by the process simulation. In the device simulation, electrical conditions to be applied on the semiconductor device externally are also entered to the device simulator, to obtain the electrical characteristics of the semiconductor device. Thus obtained electrical characteristics are checked on whether they meet the desired conditions. If they do, fabrication processes start to fabricate actual devices. If they don't and therefore it is decided that the original fabrication processes are not appropriate to fabricate a desired device, the fabrication process conditions or the process order are changed, to carry out process simulation again and enter the process simulation results to a device simulator for device simulation. This step is repeated until device fabrication processes are obtained which meet the desired characteristics, to decide appropriate fabrication processes.
To design and develop a semiconductor device by use of such process simulation and device simulation, it is necessary for engineers to work out a better procedure and conditions if fabrication procedure and conditions previously selected as an input to a process simulator are decided not to meet the desired specifications. However, the fabrication of the fine-patterned elements of recent LSIs requires few hundreds of process steps, and various impurities are introduced into the semiconductor layers or overlying thin films. Moreover, a final device structure is obtained after many heat treatment steps during the sequence of these process steps. With this, it is difficult to decide which ones of those process steps should be changed to obtain the desired structure based on such obtained final device structure.
Also, if the process simulator could output exactly the same structure as an actually fabricated semiconductor device and, likewise, the device simulator could calculate exactly the same characteristics as those in the case of actual voltage application, those two types of simulation alone would decide a method of fabricating a desired semiconductor device. However, these simulations are limited in what they can do alone. Actually, there are a lot of problems yet to be made clear such as chemical changes in materials during fabrication. Further, there are many fabrication conditions that cannot be controlled by the fabrication equipment. Those problems have significant effects on the device structure during fabrication, and the process simulation will not provide in all cases the same device structure as actual ones. In device simulation, also, the factors determining the electron behavior in the semiconductor and other physical phenomenon during application of voltage on the semiconductor device are not made clear yet, so that the characteristics assumed by device simulation do not always coincide with actual ones. Moreover, calculations must be executed within a reasonable time lapse by use of computer resources which are available easily as tools for design and development. That is, if simulation by use of such computer resources requires a longer time than that for actual trial fabrication of semiconductor devices, it is almost useless. To execute necessary calculations within a short lapse of time, it is impossible to calculate all structures or device behaviors, etc. from the first principle of nature within the simulators. Hence, model equations must be used in calculation of these structures and device behaviors, which incorporate parameters realizing the approximate realities. With these, a semiconductor device obtained by use of process simulation and device simulation do not always provide exactly the same characteristics as the actual one.
If a structure of a semiconductor device obtained by a process simulation has one or a plurality of unsuitable portions of its own, such as different structure from that of an actual one which will have significant effects on the device performance, it is not so much of use to enter thus obtained structure into the device simulator to obtain the electrical characteristics. To solve this problem, it will be necessary in such simulation to use the past data or actual measurements on a trial-fabricated structures so as to correct those unsuitable portions obtained by the simulator--if these unsuitable portions are known beforehand--which are different from the actual ones. Or it may also necessary to use some knowledge to bridge the gap between the realities and simulation results. For example, it may be appropriate to use a simulator as an auxiliary tool to decide the processes of fabricating desired semiconductor devices. Thus, it is effective to carry out device simulation after partially correcting the results of the process simulation employing such past data and actual measurements. Conventional process simulation, however, provides two-dimensional or three-dimensional structures (profiles), so that it has been extremely difficult to edit the unsuitable part of device geometry or distribution of internal impurities. And it has also been difficult to provide some tools for editing the unsuitable portions. Also, even if processes to be changed are known beforehand, in order to carry out simulation with some changed conditions, it has been necessary to perform calculations as many times as the number of the conditions of the concerned processes. Namely, at least the subsequent process after the changed condition must be calculated, which covers exact electrical characteristics, even if a rough range of conditions is required. Hence, the change of condition in the prior art wasted a lot of manpower and calculation time.
FIG. 1 is a flowchart of a processing procedure for conventional process simulation to predict a final distribution profile of impurities of a semiconductor device when the energy of implanting ions of boron (.sup.11 B.sup.+) is changed to form a p-type base region of an npn bipolar transistor. The conventional process simulation shown in FIG. 1 comprises the time-series steps of:
(a) First, antimony (.sup.122 Sb.sup.+) is used as an impurity for the deeply lying high-concentration portion and, for the near-substrate surface level (rather shallowly lying) portion, phosphorus (.sup.31 P.sup.+) ions are implanted and then the device undergoes heat treatment, so that calculation is performed on the diffusion of impurities involved in the process of forming n-type collection regions; PA1 (b) To form p-type base regions, after the n-type ones are formed, boron (.sup.11 B.sup.+) ions are implanted. Here, simulation is carried out on three conditions of boron (.sup.11 B.sup.+) ion acceleration energy levels 50 keV, 60 keV, and 70 keV, after which the condition for optimal impurity profile is given, as an example. Firstly, the case that boron (.sup.11 B.sup.+) ions are implanted with 50 keV and annealed for the activation of the implanted boron (.sup.11 B.sup.+) ions which accompany an impurity diffusion is calculated; PA1 (c) Then, arsenic (.sup.75 As.sup.+) ions are implanted to form n-type emitter regions. And impurity diffusion involved in such subsequent various heat treatment processes as emitter activation, formation of inter-layer insulator films/passivation films, and metalization is calculated. Then, as shown in FIG. 2, a final impurity distribution profile of npn bipolar transistors for the acceleration energy of 50 keV (N=1) of .sup.11 B.sup.+ is obtained; PA1 (d) The same calculation is performed in the case where the acceleration energy is set at 60 keV to form base regions again (N=2); PA1 (e) The same calculation is performed in the case where the acceleration energy is set at 70 keV (N=3); and PA1 (f) When three final structure profiles against those three ion implantation energy levels are provided, the corresponding impurity distribution profiles are compared to each other, to decide the optimal condition.
The above-mentioned calculation procedure is more specifically described with respect to the flowchart shown in FIG. 1. First, the counter value N, which indicates the number of times of simulations carried out, is set to 0 (step 101), to increase N (step 102). Next, as a pre-process, the conditions for implanting antimony (.sup.122 Sb.sup.+) and phosphorus (.sup.31 P.sup.+) ions to form n-type collector regions are read out from, for example, the data memory, to calculate impurity diffusion profile based on those ion implantation dosages Q, projected ranges Rp, standard deviations .DELTA.Rp of the projected ranges, and other prescribed boundary conditions as well as heat treatment conditions etc. (step 103). As a result, one-dimensional impurity distribution profile such as shown in FIG. 3 is obtained.
Subsequently, for ion implantation of boron (.sup.11 B.sup.+) performed as one step of p-type base region formation, the N'th ion implantation condition is read out from the data memory (step 104). Based on the corresponding dosages Q, projected ranges Rp, and other ion implantation conditions of .sup.11 B.sup.+ and also heat treatment conditions, impurity diffusion is calculated to simulate boron ion implantation (step 105). Here, N=1, 2, and 3 represent acceleration energy levels of 50 keV, 60 keV, and 70 keV respectively.
Next, as a post-process, the condition for arsenic (.sup.75 As.sup.+) ion implantation to form n-type emitter regions is read out from the data memory. Based on the boundary condition of .sup.75 As.sup.+ ion implantation such as the corresponding dosages Q and projected ranges Rp, as well as the annealing conditions of the post-implantation emitter activation, inter-layer insulator film/passivation film formation, metalization, etc., impurity diffusion is calculated (step 106).
Then, the results are output (step 107). Subsequently, it is decided whether N=3 (step 108). If N is not 3, a return is made to step 102; and if it is 3, the processing is terminated.
In process simulation for semiconductor devices, a diffusion simulation takes a major part of calculation time. In the above-mentioned example, impurity diffusion after ion implantation is numerically solved by using a diffusion equation. Generally, this "diffusion simulation" creates meshes to form discrete expressions that approximate continuity equations which describe the diffusion phenomena in semiconductor, to solve the simultaneous non-linear partial differentiation equation repetitively in a time-evolution manner. To raise a simulation accuracy, a time interval for each time loop for repetitive calculation A t must be set small to some extent, thus requiring a lot of time in diffusion simulation. As compared to diffusion simulation, "geometry simulation" generally takes a short time to terminate which obtains the changes in geometry of oxide film edges--such as the bird's-beak geometry--during LOCOS and the geometry of gate electrodes, various wiring films, trenches in semiconductor devices. A process simulator is a collection of single-process simulators for ion implantation, oxidization, diffusion, deposition, and etching processes. According to the flowchart down in FIG. 1, a series of process simulation steps which combines a number of single-process simulators in a complicated manner are calculated repetitively each time a part thereof is changed. That is, in the flowchart for conventional simulation shown in FIG. 1, to perform calculation as to three ion implantation conditions for p-type base region, time-consuming diffusion simulation comprising a series of calculations must be three times carried out from the beginning, for each of four elements (arsenic, boron, phosphorus, and antimony).
More simply describing, since there are to be carried out a total of three heat treatment for antimony (.sup.122 Sb.sup.+) and phosphorus (.sup.31 P.sup.+) ions: first heat treatment of immediately after the implantation of antimony (.sup.122 Sb.sup.+) and phosphorus (.sup.31 P.sup.+) ions; second heat treatment after boron (.sup.11 B.sup.+) implantation; and third heat treatment after arsenic (.sup.75 As.sup.+) implantation, it is necessary to perform diffusion simulation for antimony (.sup.122 Sb.sup.+) and phosphorus (.sup.31 P.sup.+) ions three times corresponding to those three heat treatment processes. Here, each of emitter activation after arsenic (.sup.75 As.sup.+) ion implantation, inter-layer insulator-film formation, passivation-film formation, and metalization is counted as one heat treatment process. For boron (.sup.11 B.sup.+) ions, diffusion simulation must be performed two times; once for heat treatment immediately after the boron (.sup.11 B.sup.+) ion implantation and another for that after arsenic (.sup.75 As.sup.+) ion implantation. And for the arsenic (.sup.75 As.sup.+) ions, one diffusion simulation must be performed corresponding to one heat treatment just after the arsenic (.sup.75 As.sup.+) ion implantation. That is, for each of boron (.sup.11 B.sup.+) ion implantation conditions, nine (=2.times.3+2+1) times of calculations must be carried out, so that for three boron (.sup.11 B.sup.+) ion implantation conditions, a total of 27 (=3.times.9) times of calculations must be carried out.
The flowchart shown in FIG. 1 is the simplest one that focuses on only the ion implantation process for discrete npn bipolar transistors, while actual fabrication of LSIs is complicated, requiring several tens to several hundreds of processes. In order to optimize the manufacturing procedure and the process conditions for fabricating LSIs, it is necessary to first specify some processes, among a large number of fabrication processes, which seem to improve the device characteristics. However, to change the conditions for each of thus specified processes, a series of simulations must be repeated from the beginning according to the prior art. Therefore, even when the process conditions to be changed have little effects on materials introduced in other processes, calculation must be performed for all processes after the conditions are changed, resulting in a longer calculation time, higher calculation costs, and a lot of manpower.
As mentioned above, diffusion simulation in semiconductor to obtain impurity or defect-density profiles requires calculations which take the longest time than any other semiconductor process simulations. Then, according to the prior art, longer calculation times, higher costs, and larger manpowers are required because it is necessary to perform calculations from the beginning each time a part of the ion implantation conditions are changed. Moreover, diffusion simulation needs to set the time interval for each time loop for repetitive calculations .DELTA.t at a small value to achieve a highly accurate calculation, and even a super-computer can take two hours of its CPU time to perform even 0.07 minute of heat treatment time, for example. That is, highly accurate process simulation takes even longer time of calculations than a actual trial fabrication of LSIs, resulting in being useless in simulation.